Welcome to Riscduino’s documentation!


Riscduino is a Open source, 32 bit RISC V based SOC design targetted to pin compatible with arudino platform. This project uses only open source tool set for RTL to GDS implementations. The SOC follows openroad/openlane flow and development environment is compatible with efabless/carvel MPW methodology.

The Github Repo could be found here and database include all the RTL, Verification and Silicon implementation scripts. * Riscdino Single Core database * Riscdino Dual Core database * Riscdino Quad Core database

The documentation contains the following chapters:

  • Description contains the general information about the Riscduino SoC,

  • getting-started contains the general information about how to use the Riscduino SoC,

  • tool-versioning contains the tool versions prefered for usage with the current Riscduino SoC,

  • quick start guide contains a guide on how to get quickly started with using Riscduino SoC without many details,

  • riscduino-with-openlane contains information on how to build your user project with OpenLANE inside the Riscduino SoC,

  • MPW Shuttle contains information about riscduino project in different MPW shuttle

  • Simulation contains information on how to simulate,

  • Pinout description describes the pinout of the SoC,

  • RISCV describes the RISCV configuration,

  • qspi describes the SPI configuration,

  • uart describes the UART interface,

  • usb1.1 describes the USB1.1 host interface,

  • memory-mapped-register lists the memory mapped registers by address,

  • references contains list of references,

  • further-work lists things to be added to the documentation.